This invention relates generally to photolithography systems for semiconductor processing, and more particularly to such a system for increasing overlay accuracy.
Patterning is one of the basic steps performed in semiconductor processing. It also referred to as photolithography, masking, oxide or metal removal, and microlithography. Patterning enables the selective removal of material deposited on a semiconductor substrate, or wafer, as a result of a deposition process. For example, as shown in FIG. 1A, a layer 104 has been deposited on a substrate 102. After the photolithography process is performed, as shown in FIG. 1B, some parts of the layer 104 have been selectively removed, such that gaps 106a and 106b are present within the layer 104. A photomask, or pattern, is used (not shown in FIG. 1B) so that only the material from the gaps 106a and 106b are removed, and not the other portions of the layer 104. The process of adding layers and removing selective parts of them, in conjunction with other processes, permits the fabrication of semiconductor devices.
Alignment is critical in photolithography and deposition, as well as in other semiconductor processes. If layers are not deposited properly, or if they are not selectively removed properly, the resulting semiconductor devices may not function, relegating them to scrap, which can be costly. Such misalignment, or overlay shift, is shown in FIG. 2. The layer 204 may or may not be deposited in a properly aligned configuration on the substrate 202, whereas subsequent deposition layers 206a, 206b, . . . , 206n are misaligned. This is indicated by the reference marks 210a, 210b, . . . , 210n, which are shown in FIG. 2 for illustrative clarity only. The reference marks 210a, 210b, . . . , 210n, should substantially align over the alignment marks 208 of the substrate 202, but they do not.
In comparison to FIG. 2, correctly aligned layers are shown in FIG. 3. The semiconductor wafer 202 has alignment marks 208. The layer 204 is aligned thereupon. Similarly, the layers 206a, 206b, . . . , 206n are deposited upon the layer 204, without any, or with minimal, overlay shift. This is indicated by the reference marks 210a, 210b, . . . , 210n aligning with the alignment marks 208 of the wafer 202.
Alignment errors such as overlay shift are also referred to as overlay error or misalignment. A common error is a simple misplacement of a layer in the x and/or y directions. Another overlay error is rotational, where one side of the wafer is aligned, but patterns become increasingly misaligned across the wafer. Other misalignment problems associated with masks and stepper aligners are run-out and run-in. These problems arise when the chip patterns are not formed on the mask on constant centers, or are placed on the chip off center. The result is that only a portion of the mask chip patterns can be properly aligned to the wafer patterns, such that the pattern becomes progressively misaligned across the wafer.
A common rule of thumb is that circuits with micron or sub-micron feature sizes must meet registration tolerances of one-third the minimum critical feature size. An overlay budget is therefore determined for the total circuit. The overlay budget is the allowable accumulated alignment error for the entire mask set. For example, for a 0.35-micron product, the allowable overlay budget is usually about 0.1 micron.
Overlay error can thus be caused by limitations in scanner or stepper stage accuracy, limitations in magnification accuracy, lens distortion, lens aberrations, such as focus, spherical, coma, and astigmatism aberrations, as well as other limitations, errors, distortions, and aberrations. Scanners and steppers are semiconductor exposure equipment, or tools, used to align a photomask over a semiconductor wafer, and then expose the wafer through the photomask. Such equipment usually has a tolerance range or otherwise has a limited accuracy, such that overlay error can result. Limitations in magnification accuracy result from the masks have a greater size than the resulting exposed image on the wafer, resulting in overlay error. Distortions and aberrations in the lenses of scanners and steppers also cause overlay error.
Conventional approaches to correct overlay error include adjusting the stage, magnification, and/or field rotation and translation to compensate for overlay errors between different layers being deposited and/or exposed. That is, between the deposition and/or exposure of different layers on the semiconductor wafer, scanner and stepper parameters such as the stage, magnification, and field rotation and translation may be varied to account and compensate for and correct overlay error. However, typically there is residual overlay error that cannot be corrected. For instance, the use of different exposure tools and equipment for different layers of the semiconductor device can be responsible for residual overlay error. Different scanners and steppers have different types of lens, with specific signatures of distortion and aberrations, causing pattern placement error.
Matching different exposure tools to one another is a difficult process, because different scanners and steppers have different overlay specifications. As an example, one scanner may have an overlay specification of 35 nanometers (nm), whereas another scanner may have an overlay specification of 55 nm. Even if these two scanners can be theoretically matched, tolerances in their overlay accuracy may further impede matching in actuality. For instance, the former scanner may actually have an overlay specification of 20 nm, whereas the latter scanner may actually have a specification of 45 nm. Matching the scanners in theory, in other words, still causes overlay error in actuality.
FIG. 4 shows an example of such a conventional two-exposure tool photolithography system 400. The system includes a pre-exposure track 402, an exposure tool 404, and a post-exposure track 406 for a front-end wafer 412A, and a pre- and post-exposure track 408 and an exposure tool 410 for a back-end wafer 412B. The back-end wafer 412B can be the front-end wafer 412A after it has been processed by the pre-exposure track 402, the exposure tool 404, and the post-exposure track 406. The tracks 402, 406, and 408 are tracks in that a continual number of wafers can be moved through them in an automated line approach. The exposure tool 404 typically has different overlay specifications than that of the exposure tool 410, such that use of the two tools 404 and 410 results in residual overlay error.
The pre-exposure track 402 handles processes that affect the photoresist prior to exposure by the exposure tool 404. These include applying the photoresist, and soft baking the photoresist. Photoresist application is usually by spinning photoresist onto the semiconductor wafer. Spinning may be static, dynamically dispensed, dispensed by a moving arm, manually spun, and/or automatically spun, among other approaches. Furthermore, a backside coating may be applied, which is coating the back of the wafer with photoresist. Soft baking is a heating operation to evaporate a portion of the solvents in the photoresist. The resist film is still soft after the soft bake, as opposed to being baked to a varnish-like finish. Soft baking can be accomplished by convection ovens, manual hot plates, in-line single-wafer hot plates, moving-belt hot plates, moving-belt infrared ovens, microwave baking, and/or vacuum baking, among other approaches.
The exposure tool 404 usually performs both alignment and exposure. Alignment is the position of the required image on the wafer surface, whereas exposure is the encoding of the image in the photoresist layer by exposing light or another radiation source. The exposure tool 404 may be or include a stepper or a scanner. Different types of aligners include optical aligners, such as contact, proximity, scanning projection, and stepper aligners, and non-optical aligners, such as x-ray and e-beam aligners.
The post-exposure track 406 handles processes that affect the photoresist after exposure by the exposure tool 404. These include developing the photoresist to remove the exposed photoresist, and hard baking the remaining, undeveloped and unexposed photoresist. Development techniques are designed to leave in the resist layer an exact copy of the pattern that was on the photomask or reticle. Development may be wet development, such as immersion, spray development, puddle development, and plasma descumming, or dry development, which is also known as plasma development. Hard baking is a heating operation to evaporate a portion of the solvents in the photoresist, similar to soft baking. However, the goal of hard baking is to achieve good adhesion of the resist to the wafer surface. Like soft baking, hard baking may be performed by convection ovens, in-line and manual hot plates, infrared ovens, moving-belt conduction ovens, and vacuum ovens.
The pre- and post-exposure track 408 includes the functionality of both the pre-exposure track 402 and the post-exposure track 404, but for the back-end wafer 412B instead of the front-end wafer 412A. The consolidation of pre-exposure and post-exposure functionality into a single track 408 is shown for example purposes only. The dual functionality of the track 408 could also be separated into two single tracks, like the tracks 402 and 404 are for the front-end wafer 412A. Similarly, he exposure tool 410 assumes the functionality of the exposure tool 404, but for the back-end wafer 412B instead of the front-end wafer 412A.
Ideally, a single scanner or stepper is used to expose all critical layers of a semiconductor device, which are the layers in which critical dimensions (CD""s) are present. However, in the prior art, it is not possible to use a single machine to expose all the critical layers. For example, to compensate for potential contamination between layers, fabrication of semiconductor devices that use copper usually employs one scanner or stepper for front-end processes, and another scanner or stepper for back-end processes. Front-end processes are those that process first layers of a device, whereas back-end processes are those that process the last layers of a device. Since overlay error must be significantly reduced as semiconductor feature size is reduced, to 0.13 micron and below, the inability to compensate for residual overlay error becomes a serious problem in semiconductor device fabrication.
Therefore, there is a need to improve overlay accuracy between layers of a semiconductor device, especially such layers that are critical. Such an improvement in accuracy should decrease residual overlay error. This improvement in overlay accuracy may also result from using a single scanner, stepper, or other exposure tool. For these and other reasons, there is a need for the present invention.
The invention relates to a semiconductor photolithography system to improve overlay accuracy. Such a system can include an exposure tool, at least one track, and a number of photoresist modules. The exposure tool performs functionality related to both at least a front-end and a back-end wafer. Each track has one or more paths to and from the exposure tool. The photoresist modules each perform functionality related to photoresist, on only either the front-end wafer or the back-end wafer, not both. Each module is located on one of the tracks.
In one two-track system of the invention, there is a first track for the front-end wafer and a second-track for the back-end wafer. The first track has a single path for the front-end wafer, whereas the second track has a single path for the back-end wafer. In one one-track system of the invention, there is only a single track that has two paths. One of the paths is for the front-end wafer, and the other of the paths is for the back-end wafer.
The invention provides for advantages over the prior art. Overlay accuracy is improved because residual overlay error is decreased. Since front-end and back-end wafer processing is performed on the same exposure tool, no matching between disparate exposure tools is required. Still other advantages, embodiments, and aspects of the invention will become apparent by reading the detailed description that follows, and by referencing the attached drawings.